Analogue Designer, CMOS Modelling

Job Description

Job Title: Staff Analogue Designer, CMOS Modelling. Location: Oxford, England, United Kingdom

Own the full-chip modelling strategy, including model architecture, abstraction levels, accuracy targets, sign-off criteria, and implementation across the IC development flow.
Develop Verilog-A and Verilog-AMS models for analogue blocks including references, DACs, switches, regulators, and clock distribution.
Assemble analogue models into a simulatable full-chip model;
Build real-number models using SystemVerilog nettype/UDN and legacy wreal for high-speed digital verification and regression.
Derive behavioural models from first-principles mathematics, including transfer functions, Z-parameter network descriptions, and MATLAB analysis.
Implement robust and convergent Verilog-A models with appropriate tolerances.
Define and run model-versus-schematic correlation to keep models aligned with design releases.
Incorporate measured silicon behaviour back into the modelling flow.
Establish mixed-signal co-simulation and regression using Cadence AMS Designer, Xcelium, and Spectre.
Contribute to block-level design reviews;
Mentor engineers on modelling practices and improve modelling standards across the team.
Determine appropriate modelling fidelity and clearly define what each model does and does not represent.
Support cryo-CMOS ASIC development for trapped-ion quantum processors and contribute directly to research and development milestones.

10+ years of deep analogue and mixed-signal design and modelling experience.
Experience developing models used in production tapeout flows is preferred.
Expert-level experience with Verilog-A and Verilog-AMS.
Strong experience with real-number modelling;
Ability to derive models from mathematical equations and implement them end to end.
Strong mathematical foundations in linear systems, Laplace and z-domain analysis, network Z-parameters, noise, and non-linearity.
Experience working in a production Cadence environment;
Experience with simulation tools such as Virtuoso, Spectre, Xcelium, and AMS Designer or similar.
Experience with SystemVerilog and MATLAB or Python/NumPy for analysis and model validation.
Ability to collaborate effectively with designers, verification engineers, and system engineers in a highly technical environment.

Preferred:

Experience with cryogenic or other extreme-environment silicon.
Experience with space-related silicon or electronics.
Experience modelling analogue blocks and complete mixed-signal ICs.
Experience validating models against schematic and measured silicon;
Experience contributing to modelling standards, methodology, and sign-off criteria.
Experience supporting complex IC development and tapeout decisions.

Compensation is determined based on education, qualifications, experience, office location, market data, and internal equity.
Comprehensive medical, dental, and vision plans.
Matching 401(k).
Unlimited paid time off.
Paid holidays.
Parental and adoption leave.
Legal insurance.
Home technology stipend.

IonQ is an equal opportunity employer committed to fair treatment, access, opportunity, and advancement.
The position involves access to technology subject to U.S. export control and government contract restrictions.
Certain applicants may need to verify U.S. Person status, obtain an applicable license, or qualify under a license exception for access to export-controlled technology.
Additional immigration-status questions may be required for export-control and compliance purposes;
Employment is subject to applicable pre-employment background and risk screening.
Screening may include identity, employment history, education and qualifications, sanctions and restricted-party checks, adverse media, public records, and other legally permitted checks.
Applicants must provide the required privacy and background-check consents as part of the application process.

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