Analog Mixed-Signal Design & Modelling Engineer

Job Description

Job Title: Senior Staff Analog Mixed-Signal Design and Modelling Engineer. Location: Oxford, England, United Kingdom

• Hybrid, with the option to work remotely a few days per week
• Travel: Up to 5%

Responsibilities:

• Own the full-chip modelling strategy, including model architecture, abstraction levels, accuracy targets, and sign-off criteria.
• Design and own analog and mixed-signal blocks including references, DACs, switches, regulators, and clock distribution from specification through schematic design.
• Own top-level integration, define block interfaces and specifications, assemble the top level, and run full-chip mixed-signal simulations.
• Develop Verilog-A and Verilog-AMS models of analog blocks and integrate them into a simulatable full-chip model.
• Build real-number models that allow the full chip to run efficiently in digital verification and regression;
• Derive models from first-principles mathematics, including transfer functions, Z-parameter network descriptions, and MATLAB analysis.
• Define and run model-versus-schematic correlation and keep models synchronized with design releases.
• Incorporate measured silicon behavior into models and block designs.
• Establish mixed-signal co-simulation and regression using Cadence AMS Designer, Xcelium, and Spectre.
• Lead block-level design reviews and mentor engineers in circuit design and modelling.
• Establish design and modelling standards and sign-off criteria for the development program;
• Develop trusted models that support tape-out decisions and improve the modelling capabilities of the engineering team.

Qualifications:

• Typically 10+ years of deep analog and mixed-signal design and modelling experience.
• Proven experience designing analog blocks through silicon validation and production tape-out.
• Expert transistor-level design experience with precision analog blocks such as references, DACs, regulators, switches, and clock distribution.
• Experience with PVT and Monte Carlo analysis, layout, and silicon validation;
• Expert experience with Verilog-A and Verilog-AMS and strong real-number modelling skills.
• Multiple tape-outs with responsibility for block design and top-level integration.
• Experience with silicon bring-up and bench characterization.
• Strong mathematical foundations in linear systems, Laplace and Z-domain analysis, network Z-parameters, noise, and non-linearity.
• Production experience with Cadence Virtuoso, Spectre, Xcelium, and AMS Designer or similar co-simulation environments.
• Experience with parasitic extraction and post-layout sign-off.
• Experience with SystemVerilog and Python or MATLAB for analysis and model validation;
• Experience writing scripts to automate model generation, checking, and regression.
• Ability to determine the appropriate modelling fidelity and clearly communicate model capabilities and limitations across design, verification, and systems teams.

Preferred:

• Experience with Cryogenic silicon, space electronics, or other extreme-environment systems.
• Experience designing beyond foundry model validity using measured device data.
• Experience deriving models from equations and implementing them end to end.
• Experience aligning designers, verification engineers, and systems engineers around modelling requirements and expectations.

Benefits and Compensation:

• Compensation is determined based on education, qualifications, experience, office location, market data, and internal team equity.
• Comprehensive medical, dental, and vision plans.
• Matching 401(k).
• Unlimited paid time off.
• Paid holidays.
• Parental and adoption leave.
• Legal insurance.
• Home technology stipend.

Other Information:

• The role involves technology subject to U.S. export control and government contract restrictions.
• Employment may require verification of U.S. Person status, obtaining an applicable export license, or confirming a license exception.
• Additional immigration-status questions may be required for export-control compliance;
• Pre-employment background and risk screening may include identity, employment history, education, sanctions and restricted-party screening, adverse media, public records, and legally accessible criminal or court records.