Formal Verification Engineer

Job Description

Job Title: Formal Verification Engineer. Location: Bangalore, Karnataka, India

Responsibilities:

• Develop verification environments, testbenches, and test cases for processor and ASIC designs
• Perform formal and functional verification of logic blocks
• Collaborate with design teams to debug and resolve logic issues'
• Use formal verification tools and methodologies to ensure design quality
• Analyze failures, triage issues, and improve verification coverage

Qualifications:

• Master’s degree in Engineering or related field
• 5 to 10 years of experience in formal or functional verification
• Strong knowledge of HDLs such as Verilog, VHDL, or SystemVerilog
• Programming experience in Python and understanding of processor microarchitecture
• Experience in debugging, testbench development, and verification workflows

Preferred:

• Ability to lead verification efforts and drive coverage closure
• Experience handling complex verification scenarios
• Participation in high-level design discussions;
• Strong communication skills and ability to work in global teams

Benefits and Compensation:

• Opportunity to work on advanced systems contributing to quantum computing and AI
• Exposure to cutting-edge processor and hardware technologies
• Career growth in a global engineering environment

Other Information:

• No travel required
• Day shift role;
• Equal opportunity employer with inclusive workplace policies